In a direct memory access (DMA) transmission technology, a hardware apparatus, e.g. a hard-disk drive or a network interface card, can directly access data from a main memory without the facilitation of a microprocessor. Hence, the DMA transmission can efficiently reduce the loading of the microprocessor and enhance the data transmission performance.
Please refer to FIG. 1A which is a schematic circuit block diagram illustrating a conventional computer structure operating by using the DMA. The personal computer includes a microprocessor 10, a memory 11, a chip set 13 and a network interface card (NIC) 12 including a DMA controller 121. When the operating system (OS) is going to transmit a data file to the NIC 12, the microprocessor 10 is interrupted to transmit the data file in a data packet format to the memory 11 to be stored via the chip set 13, and then continues the suspended work. The DMA controller 121 of the NIC 12 directly reads the data packets associated with the data file from the memory 11 via the chip set 13 after receiving the start address of the data file. The data is stored into a first-in first-out (FIFO) buffer 122 of the DMA controller 121.
Please refer to FIG. 1B which is a schematic diagram illustrating a conventional storage format of the main memory 11 for storing data packets. The main memory 11 includes two major portions, i.e. a descriptor and a data buffer for storing data packets. The descriptor includes the information of the stored address of a data packet in the data buffer, data length, data status and a descriptor address of next data packet.
Typically, after reading the descriptor of a data packet from the memory 11, the DMA controller 121 picks up the data packet from the data buffer according to the stored address of the data packet, and stores the data packet to the FIFO buffer 122 of the DMA controller 121. Then, the NIC 12 asserts a signal to the descriptor of the data packet to re-write the data status of the data packet. Further, the NIC 12 locates the descriptor of next data packet according to the information included in the descriptor of the preceding data packet, and receives the subsequent data packet according to the corresponding descriptor. The data status of the data packets received by the NIC 12, which is recorded in the descriptor, is checked by the microprocessor 10 to determine whether the data packet transmission is normal or not.
Since the above data transmission process is performed on the basis of the information recorded in the descriptor, the possible errors associated with the descriptor will result in abnormal transmission. The possible errors may include the error occurring inside the hardware and the error occurring in the data-reading process of the DMA controller. For example, due to the error occurring inside the hardware, the DMA controller may read wrong descriptor so as to result in a transmission error. For another example, due to the error occurring in the data-reading process of the DMA controller, the DMA controller may pick up a wrong data packet from a data buffer that does not comply with the current descriptor. Such transmission errors will cause the DMA controller to receive incorrect following data packets or access data packets from an invalid region. Practically, even though the above errors occur, the operating system will not notice until the file transmission is failed or the transmitted file is wrong. At this moment, the driver will assert a reset signal to the NIC to re-transmit the data packets. Since the operating system cannot timely detect the above transmission problems, the data transmission efficiency is adversely affected.
Therefore, the object of the present invention is to quickly determine whether the descriptor address to be read by the DMA controller is correct or not.